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DRAM Controller Design Assignment by Dr-Raghad Al-Faham is a document available to read on EtoBox.

This document describes an assignment to design a DRAM controller circuit to interface between a CPU and bank of 1Mbit DRAM chips. The controller must handle read and refresh cycles over a 4 clock cycle bus. It is provided the CPU clock, address, address valid and hold acknowledge signals. It must output the hold request, row access strobe, column access strobe and 10-bit multiplexed DRAM address signals according to the timing diagram. The assignment is to write synthesizable VHDL code for the controller,

Author

Dr-Raghad Al-Faham

Language

EN