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RIVER: Reconfigurable Flow and Fabric for Real-Time Signal Processing on FPGAs by Christian Brugger; Dominic Hillenbrand; Matthias Balzer is a Computer Science article available to read on EtoBox.

What is RIVER: Reconfigurable Flow and Fabric for Real-Time Signal Processing on FPGAs about?

For high-performance embedded hard-real-time systems, ASICs and FPGAs hold advantages over general-purpose processors and graphics accelerators (GPUs). However, developing signal processing architectures from scratch requires significant resources. Our design methodology is based on sets of configurable building blocks that provide storage, dataflow, computation, and control. Based on our building blocks, we generate hundreds of thousands of our dynamic streaming engine processors that we call DSEs. We store our DSEs in a repository that can be queried for (online) design space exploration. From this repository, DSEs can be downloaded and instantiated within milliseconds on FPGAs. If a loss of flexibility can be tolerated then ASIC implementations are feasible as well. In this article we focus on FPGA implementations. Our DSEs vary in cores, computational lanes, bitwidths, power consumption, and frequency. To the best of our knowledge we are the first to propose online design space exploration based on repositories of precompiled cores that are assembled of common building blocks. For demonstration purposes we map algorithms for image processing and financial mathematics to DSEs an

Who reads RIVER: Reconfigurable Flow and Fabric for Real-Time Signal Processing on FPGAs?

Author

Christian Brugger; Dominic Hillenbrand; Matthias Balzer

Publisher

ACM

Published

2014

Language

EN

Field

Computer Science (Physical Sciences)