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6T SRAM Cell Design in 32nm Technology by Nguyễn Thị Như Quỳnh is a document available to read on EtoBox.

What is 6T SRAM Cell Design in 32nm Technology about?

This document presents a comparative study of various 6T SRAM cell layouts at the 32nm technology node, evaluating four symmetric topologies in terms of area efficiency, power dissipation, and read/write delay. The study finds that the thin-cell design outperforms others in power and delay performance while maintaining a compact area. Simulations demonstrate that the type 4 cell achieves the best write delay, while read delays are similar across all cell types due to reliance on external circuitry.

Author

Nguyễn Thị Như Quỳnh

Language

EN