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Low Power 8T SRAM Design for AI Cache by deberjeet usham is a document available to read on EtoBox.

What is Low Power 8T SRAM Design for AI Cache about?

The document describes a proposed 8T SRAM cell architecture that aims to improve on existing SRAM cell designs. It discusses limitations of traditional 6T SRAM cells related to noise margins, power consumption, speed, and robustness to variations. Prior reported SRAM cell architectures are reviewed that focused on improving certain parameters. The proposed 8T cell is simulated and its performance metrics, such as read/write delays, power consumption, and noise margins, are compared to other designs to demon

Author

deberjeet usham

Language

EN