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What is Hardware Optimization for Complex Multiplication about?

This document summarizes a research paper presented at the IEEE International Conference on Computer, Communication and Control (IC4-2015). The paper proposes optimizations to the hardware implementation of complex multiplication schemes for digital signal processing applications. Specifically, it discusses reducing the number of multipliers used in conventional complex multiplication from four to three multipliers, saving area. It also analyzes the tradeoff of adding adders to further reduce hardware by u

Author

Humira ayoub

Language

EN