About this document
Understanding ASM Charts in Digital Design by Ar-Jay Madeja is a document available to read on EtoBox.
The document describes an experiment to design an algorithmic state machine (ASM) to test 4-input NAND gates. The ASM will have up to 4 states: 1) Wait for start signal, 2) Initialize outputs and clear counter, 3) Test gate and set outputs, 4) Return to step 1. The data processor will generate all input combinations, compare outputs to a reference gate, and set pass/fail flags. The control unit will be implemented with a multiplexer and decoder using up to 4 states.
- Author
- Ar-Jay Madeja
- Language
- EN