About this scholarly article

Proceedings of the IEEE 1998 Custom Integrated Circuits Conference (Cat. No.98CH36143) - Combined transistor sizing with buffer insertion for timing optimization by Yanbin Jiang, ; Sapatnekar, S.S.; Bamji, C.; Juho Kim, is a scholarly article available to read on EtoBox.

Author

Yanbin Jiang, ; Sapatnekar, S.S.; Bamji, C.; Juho Kim,

Publisher

IEEE

Published

1998