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This document discusses wafer bonding of processed silicon CMOS VLSI and gallium arsenide for mixed technology integration. It provides background on optoelectronic and mixed technology integration. The research aims to bond processed silicon wafers simulating full backend processing to gallium arsenide wafers, carrying out the entire process below 450°C to be compatible with silicon CMOS. The goal is to bond fully processed wafers and test interconnect feasibility through the bond interface.

Author

aidasfar744

Language

EN