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Power Aware Testing in VLSI Design by sambhunit is a document available to read on EtoBox.

What is Power Aware Testing in VLSI Design about?

The document discusses power aware testing of VLSI chips. It notes that VLSI chips contain many transistors and feature sizes smaller than 100nm increase the likelihood of defects. During testing, switching activity and parallel testing can lead to excessive power dissipation compared to normal operation. The document also states that testing is one of the most expensive parts of the design cycle and that power must now be considered as a critical parameter for developing low power system tests.

Author

sambhunit

Language

EN