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This paper presents a fully synthesizable fractional-N injection-locked PLL implemented in 65nm CMOS that achieves RMS jitter of 1.2ps and 0.3ps at 1GHz output for fractional-N and integer-N operation respectively. A true arbitrary nonlinearity calibration scheme is proposed for synthesizable digital-to-time conversion, along with extensive digital calibration of the PLL. The PLL consumes 2.5mW and 2.2mW in fractional-N and integer-N modes respectively, corresponding to a figure of merit of -234.4dB and -24

Author

Suyog Dhakne

Language

EN