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This document presents a design for a 32-bit Dadda multiplier that utilizes 4:2 compressors and a Han-Carlson adder to enhance speed and reduce delay compared to the traditional Kogge-Stone adder. The proposed design achieves significant improvements in performance while maintaining lower hardware complexity and power consumption. Simulation results indicate that the new design offers a balanced trade-off suitable for both speed- and area-constrained applications.

Author

Barma Hanumantharao

Language

EN