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What is 8-bit Segmented Current Steering DAC about?

This paper presents a 500 MSPS 8-bit segmented Current Steering Digital to Analog Converter (CS-DAC) designed using 180 nm CMOS technology, achieving a Spurious Free Dynamic Range (SFDR) greater than 66 dB. The architecture employs a 5+3 segmentation approach to balance performance and area, utilizing unary DACs for the most significant bits and binary DACs for the least significant bits. The design includes an on-chip voltage reference circuit for biasing current cells, ensuring high linearity and minimal

Author

Deepika

Language

EN