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Can I read Design and Analysis of (5, 10) Regular LDPC Encoder Using MRP Technique on EtoBox?
Design and Analysis of (5, 10) Regular LDPC Encoder Using MRP Technique by V. Nandalal; V. Anand Kumar is a Engineering article available to read on EtoBox.
What is Design and Analysis of (5, 10) Regular LDPC Encoder Using MRP Technique about?
An efficient compact encoding process with the pipelining design of Low Density Parity Check (LDPC) Encoder with a two stage, three stage and Maximal Rate Pipelining (MRP) structures are proposed in this work. Comparatively, LDPC encoding is more complex than decoding. The complexity mainly referred to the mathematical computation involved in the design of LDPC encoder. There are several methods used to design reduced parity check matrix, one of the methods involved is the Gauss Elimination method. Conventional and wave pipelining techniques are implemented to overcome the disadvantages of the area, latency, etc., The designed architectures are synthesized in SYNOPSYS tool and implemented in the XC3S-250E FPGA device. The overheads like power and area are efficiently reduced by wave pipelining and their efficiency can be proved by synthesis report. This showcases that the LDPC Encoders require less memory by using MRP structure.
Who reads Design and Analysis of (5, 10) Regular LDPC Encoder Using MRP Technique?
It is typically read by researchers, students, and practitioners in Engineering.
- Author
- V. Nandalal; V. Anand Kumar
- Publisher
- Springer Science and Business Media LLC
- Published
- 2021
- Language
- EN
- Field
- Engineering (Physical Sciences)