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Characterization of logic circuit techniques and optimization for high-leakage CMOS technologies by Phillip Chin; Charles A. Zukowski; George D. Gristede; Stephen V. Kosonocky is a Engineering article available to read on EtoBox.

What is Characterization of logic circuit techniques and optimization for high-leakage CMOS technologies about?

Channel subthreshold and gate leakage currents are predicted by many to become much more significant in advanced CMOS technologies and are expected to have a substantial impact on logic circuit design strategies. To reduce static power, techniques such as the use of monotonic logic and management of various evaluation and idle modes within logic stages may become important options in circuit optimization. In this paper, we present a general, multilevel model for logic blocks consisting of logic gates that include a wide range of options for static power reduction, in both the domains of topology and timing. Existing circuit techniques are classified within this framework and experiments are presented showing how aspects of performance might vary across this range in a hypothetical technology. The framework also allows exploration of optimal mixing of techniques.

Who reads Characterization of logic circuit techniques and optimization for high-leakage CMOS technologies?

Author

Phillip Chin; Charles A. Zukowski; George D. Gristede; Stephen V. Kosonocky

Publisher

Elsevier Science; Elsevier ; Elsevier BV (ISSN 0167-9260)

Published

2005

Language

EN

Field

Engineering (Physical Sciences)