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Stochastic Interconnect Layout Sensitivity Model by Payman Zarkesh-Ha; Ken Doniger is a scholarly article available to read on EtoBox.

What is Stochastic Interconnect Layout Sensitivity Model about?

Semiconductor manufacturing yield is determined by the defect density and critical area i.e. that portion of the layout in which the occurrence of a defect results in yield loss. In this paper, we define layout sensitivity as the ratio of critical area to the layout area. Utilizing the basic probability theory, a rigorous derivation of layout sensitivity for random logic network is performed. This model is compared to actual critical area distributions for a modern microprocessor design. A methodology to calculate the layout sensitivity pattern for a complex layout is proposed.

Author

Payman Zarkesh-Ha; Ken Doniger

Publisher

ACM

Published

2007

Language

EN