About this scholarly article

International Electron Devices Meeting 2000. Technical Digest. IEDM (Cat. No.00CH37138) - 30 nm physical gate length CMOS transistors with 1.0 ps n-MOS and 1.7 ps p-MOS gate delays by Chau, R.; Kavalieros, J.; Roberds, B.; Schenker, R.; Lionberger, D.; Barlage, D.; Doyle, B.; Arghavani, R.; Murthy, A.; Dewey, G. is a scholarly article available to read on EtoBox.

Author

Chau, R.; Kavalieros, J.; Roberds, B.; Schenker, R.; Lionberger, D.; Barlage, D.; Doyle, B.; Arghavani, R.; Murthy, A.; Dewey, G.

Publisher

IEEE

Published

2000

Language

EN