About this scholarly article

2002 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.02CH37302) - Crosstalk delay analysis of a 0.13-μm-node test chip and precise gate-level simulation technology by Sasaki, Y.; Satoh, M.; Kuramoto, M.; Kikuchi, F.; Kawashima, T.; Masuda, H.; Yano, K. is a scholarly article available to read on EtoBox.

Author

Sasaki, Y.; Satoh, M.; Kuramoto, M.; Kikuchi, F.; Kawashima, T.; Masuda, H.; Yano, K.

Publisher

IEEE

Published

2002