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About this Engineering article
An 800 MS/s Dual-Residue Pipeline ADC in 40 nm CMOS by Vecchi, D.; Mulder, J.; van der Goes, F.M.L.; Westra, J.R.; Ayranci, E.; Ward, C.M.; Jiansong Wan; Bult, K. is a Engineering article available to read on EtoBox.
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- Author
- Vecchi, D.; Mulder, J.; van der Goes, F.M.L.; Westra, J.R.; Ayranci, E.; Ward, C.M.; Jiansong Wan; Bult, K.
- Publisher
- IEEE; Institute of Electrical and Electronics Engineers; Institute of Electrical and Electronics Engineers (IEEE) (ISSN 0018-9200)
- Published
- 2011
- Field
- Engineering (Physical Sciences)