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High PSR LDO Design for SOCs by Jason Gong is a document available to read on EtoBox.
This article presents a novel design for a linear low-dropout regulator (LDO) that achieves a power supply rejection (PSR) of over 68 dB up to 2 MHz while consuming only 5.6 μA of quiescent current. The design utilizes a current-mode feedforward ripple canceller (CFFRC) amplifier to enhance PSR across a wide range of loads, improving transient response and reducing the need for complex circuitry. The LDO is fabricated using a 180 nm bipolar/CMOS/DMOS process, making it suitable for high-performance applicat
- Author
- Jason Gong
- Language
- EN