About this document
VLSI Test Power Minimization Survey by p.vamshidhar reddy is a document available to read on EtoBox.
The document surveys the challenges and approaches in minimizing test power for VLSI circuits, highlighting the significant power dissipation during testing compared to normal operation. It discusses various low power testing techniques, including LFSR-based methods and design for testability (DFT) strategies, aimed at reducing energy consumption while maintaining test quality. The paper emphasizes the importance of power management in modern IC design, particularly for battery-operated devices, and present
- Author
- p.vamshidhar reddy
- Language
- EN