About this document
Vdd Scaling Impact on DCT Performance by Dr. Sampatrao L Pinjare is a document available to read on EtoBox.
The document discusses the effect of voltage scaling on different discrete cosine transform (DCT) architectures. It shows that a proposed 2-alphabet DCT architecture degrades gracefully when the supply voltage (Vdd) is scaled down from 1.0V to 0.8V, with power savings of over 60% at 0.8V, while conventional architectures fail below 0.9V. It also discusses applying the concept of critical and less-critical components to finite impulse response filters and color interpolation to enable voltage scaling.
- Author
- Dr. Sampatrao L Pinjare
- Language
- EN