About this document

TSMC Hierarchical Design Flow 3.0 by Girish Prabhu is a document available to read on EtoBox.

1. The document describes the TSMC hierarchical design flow involving multiple EDA tools including First Encounter, Physical Compiler, Apollo, and PrimeTime. 2. The flow includes prototyping at both block and top level, pre-CTS and post-CTS implementation in Physical Compiler and Apollo, and RC correlation between the two tools. 3. Final steps involve detailed routing in Apollo, full-chip signoff checks including timing analysis, DRC, LVS, and verification of effects like IR drop, crosstalk, and antenna.

Author

Girish Prabhu

Language

EN