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VL2012-13 by rao.dwh92 is a document available to read on EtoBox.
What is VL2012-13 about?
The document discusses the implementation of a power-efficient Vedic multiplier based on the Nikhilam Sutra from Vedic mathematics, aiming to reduce power consumption while maintaining performance. The proposed architecture modifies existing designs and is coded in Verilog HDL, with comparisons made against traditional multipliers in terms of area, data arrival time, and power consumption. Results indicate significant improvements in power efficiency, making it suitable for DSP applications.
- Author
- rao.dwh92
- Language
- EN