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Reference Voltage Buffer for 10-bit SAR ADC by Sofia Inacio is a document available to read on EtoBox.

This paper details the design of a reference voltage buffer (RVBuffer) for a 10-bit, 50 MS/s successive approximation register (SAR) ADC implemented in 65 nm CMOS, addressing the challenges of DAC settling time and the impact of parasitic inductances. The RVBuffer is crucial for maintaining ADC performance by isolating the DAC reference voltage from ringing effects, achieving a settling time of 692 ps and a PSRR that minimizes noise interference. Simulation results demonstrate the RVBuffer

Author

Sofia Inacio

Language

EN