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Integrated Clock Gating in VLSI Design by Naganithesh Ghattamaneni is a document available to read on EtoBox.

Integrated Clock Gating (ICG) cells are used in low power ASIC design to reduce dynamic power consumption by stopping clock signal propagation when not needed. ICG cells use a latch-and based architecture with a clock enable input to provide a glitch-free gated clock output. When the enable is high, the clock passes through; when low, clock propagation is stopped. ICG cells are preferred over simple AND gates for clock gating due to preventing glitches on the gated clock signal.

Author

Naganithesh Ghattamaneni

Language

EN