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The document presents a 32-bit Hybrid Ripple Ling Carry Adder that combines a Ling-based parallel prefix adder for the upper 16 bits and a ripple-carry adder for the lower 16 bits, optimizing performance, power, and area efficiency in VLSI designs. This hybrid structure achieves significant power savings of 12%, area reduction of 30%-40%, and a worst-case delay of 0.182 ns in a 28 nm process. The design effectively balances speed and resource utilization, making it suitable for high-performance digital syst

Author

sasinakka005

Language

EN