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10-bit 1.2 GS/s DAC Design in CMOS by Prateek Kamboj is a document available to read on EtoBox.

What is 10-bit 1.2 GS/s DAC Design in CMOS about?

This thesis presents the design of a 10-bit, 1.2 GS/s current steering digital-to-analog converter (DAC) fabricated in a 90 nm CMOS process. The DAC uses a thermometer encoder and current steering architecture with carefully designed current cells to achieve high performance. Simulation results show the DAC achieves a differential non-linearity of 0.02 LSB and integral non-linearity of 0.29 LSB with a spurious free dynamic range of 72.07 dB at 596.48 MHz input signal. The DAC design and performance are disc

Author

Prateek Kamboj

Language

EN