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The document presents the design and implementation of a low-power AI system for Indian Sign Language recognition using a neural network accelerator tailored for ResNet-50 on the ZCU102 platform with FPGA technology. It highlights the optimization strategies employed, such as data quantization and depthwise separable convolution, to enhance operational speed and reduce resource consumption while maintaining acceptable inference accuracy. The results demonstrate significant performance improvements, achievin
- Author
- hussainlearnup
- Language
- EN