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What is Low Power 12-Bit SAR ADC Design about?

The document presents a low power 12-bit 1 Msps successive approximation register (SAR) ADC featuring an improved switching procedure that significantly reduces power consumption and area occupation. The proposed design achieves an 80% reduction in average switching energy and a 50% reduction in total capacitance compared to conventional methods, with a total power consumption of only 0.72 mW. Simulation results indicate that the power dissipation of the digital control circuits can be reduced by about 50%,

Author

2024vlm001.mainak

Language

EN