About this document
2.5 Gb/s Digital CDR with Low Power by Lâm Trần Thành is a document available to read on EtoBox.
This document discusses a digital clock and data recovery circuit that employs hybrid analog/digital phase detection to achieve linear loop dynamics and eliminate nonlinearity from a bang-bang phase detector. It aims to achieve constant jitter transfer bandwidth independent of input jitter and reduce sensitivity to frequency quantization error and consecutive identical digits. The proposed architecture is compared to conventional digital CDR designs and their limitations.
- Author
- Lâm Trần Thành
- Language
- EN