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This document presents a thesis on analyzing the impact of bias temperature instability (BTI) at the sub-block level in processor datapaths. BTI is a prominent reliability issue for logic CMOS devices that worsens as transistors age. The thesis develops a novel aging-aware digital design framework using industry standard EDA tools to perform BTI analysis. Static timing analysis is used to evaluate performance metrics of aged designs and compare them to original designs. Finally, error resilient techniques a
- Author
- Bagus Hanindhito
- Language
- EN