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This document proposes and analyzes techniques to reduce leakage power in sequential circuits like D flip-flops and shift registers for use in nanoscale VLSI systems. It presents three implementations of D flip-flops and simulates them with and without applying transistor stacking, self-adjustable voltage level circuits, and reverse body biasing. Simulation results on 65nm process technology show the pass transistor D flip-flop has the lowest leakage power. Applying stacking and reverse body biasing to shif

Author

Lita Sandu

Language

EN