About this document
VHDL Code for Basic Logic Gates by ashutoshdabas17 is a document available to read on EtoBox.
The document describes experiments to design basic logic gates and arithmetic circuits using VHDL. Experiment 1 involves designing AND, OR, NOT, NAND, NOR, XOR and XNOR gates. Experiment 2 involves designing half adder and full adder circuits using different VHDL styles. Experiment 3 involves designing half subtractor and full subtractor circuits. For each circuit, the VHDL code, RTL view and simulation waveform are provided. The goal is to design the circuits using VHDL and verify their functionality throu
- Author
- ashutoshdabas17
- Language
- EN