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Spatio-Temporal Bias Tunable Readout Circuit For On-Chip Intelligent Image Processing by dhtruongvnu is a document available to read on EtoBox.
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The article presents a novel 96 × 96 array readout integrated circuit (ROIC) that allows for individual pixel bias control, enhancing infrared imaging capabilities. The design includes a capacitive transimpedance amplifier architecture and an FPGA-based test bench, enabling real-time spatio-temporal bias tuning for improved image processing. This technology aims to facilitate advanced on-chip image analysis and multispectral acquisition, particularly for infrared retina applications.
- Author
- dhtruongvnu
- Language
- EN