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What is Lab 8: Verilog FPGA Latch Design about?

This lab report describes the implementation of latches and counters on an FPGA board. Part 1 creates a gated SR latch in Verilog using structural code. Part 2 modifies this to create a gated D latch. Part 3 physically implements the gated D latch on the FPGA board using slide switches as inputs and an LED as the output. Part 4 creates a counter on the board by modifying the D latch code to include sequential logic and feedback. Performance and behavior matched simulations.

Author

api-427877684

Language

EN