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An evaluation of memory consistency models for shared-memory systems with ILP processors by Vijay S. Pai; Parthasarathy Ranganathan; Sarita V. Adve; Tracy Harton is a Computer Science article available to read on EtoBox.

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Relaxed consistency models have been shown to significantly outperform sequential consistency for single-issue, statically scheduled processors with blocking reads. However, current microprocessors aggressively exploit instruction-level parallelism (ILP) using methods such as multiple issue, dynamic scheduling, and non-blocking reads. Researchers have conjectured that two techniques, hardware-controlled non-binding prefetching and speculative loads, have the potential to equalize the hardware performance of memory consistency models on such processors.This paper performs the first detailed quantitative comparison of several implementations of sequential consistency and release consistency optimized for aggressive ILP processors. Our results indicate that hardware prefetching and speculative loads dramatically improve the performance of sequential consistency. However, the gap between sequential consistency and release consistency depends on the cache write policy and the complexity of the cache-coherence protocol implementation. In most cases, release consistency significantly outperforms sequential consistency, but for two applications, the use of a write-back primary cache and a

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Author

Vijay S. Pai; Parthasarathy Ranganathan; Sarita V. Adve; Tracy Harton

Publisher

ACM

Published

1996

Language

EN

Field

Computer Science (Physical Sciences)