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A Phase-Locked Loop Reference Spur Modelling Using Simulink by JOCOVI1987 is a document available to read on EtoBox.

Phase-locked loops (PLLs) are a commonly used module in frequency synthesizers as part of RF transceivers. This paper introduces charge pump and phase / Frequency Detector (PFD) non-idealities in the integer-N PLL behavioural model to estimate the periodic noise. The proposed model was implemented in Simulink and showed less than +-3% error when compared to transistor level simulations from Cadence Spectre.

Author

JOCOVI1987

Language

EN