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This thesis presents the design and implementation of an 8-bit Successive Approximation Register (SAR) ADC using VLSI technology, aimed at low power consumption and moderate speed for applications in AI and biomedical sensors. The system includes components such as an internal clock generator, bootstrapped sample-and-hold circuit, capacitive DAC, and dynamic comparator, achieving a maximum Effective Number of Bits (ENOB) of 7.35 at a sampling frequency of 20 MHz. The results demonstrate the feasibility of t

Author

ivanvanko1123

Language

EN