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About this Engineering article
SET/RESET Cycling-Induced Trap Creation and SET-Disturb Failure Time Degradation in a Resistive-Switching Memory by Chung, Yueh-Ting; Su, Po-Cheng; Lin, Wen-Jie; Chen, Min-Cheng; Wang, Tahui is a Engineering article available to read on EtoBox.
It is typically read by researchers, students, and practitioners in Engineering.
- Author
- Chung, Yueh-Ting; Su, Po-Cheng; Lin, Wen-Jie; Chen, Min-Cheng; Wang, Tahui
- Publisher
- IEEE; Institute of Electrical and Electronics Engineers; Institute of Electrical and Electronics Engineers (IEEE) (ISSN 0018-9383)
- Published
- 2016
- Language
- EN
- Field
- Engineering (Physical Sciences)
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