About this document
Low-Power Full Adder Circuit Design by vishwas is a document available to read on EtoBox.
The document proposes new circuits for XOR/XNOR and XOR-XNOR gates that have lower power consumption and delay. Six new hybrid 1-bit full adder circuits are also proposed based on these novel gates. Extensive simulations show the proposed designs have superior speed and power over other designs in 65nm technology. A new transistor sizing method is also presented to optimize power-delay product using particle swarm optimization with fewer iterations.
- Author
- vishwas
- Language
- EN