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4-Bit Brent Kung Adder Simulation Study by HAROON AHMED is a document available to read on EtoBox.

This document summarizes a study on simulating a 4-bit Brent Kung parallel prefix adder using Silvaco EDA tools. The study implemented the adder using basic logic gates and compound gates to compare performance. Simulation results showed that the compound gate implementation reduced power consumption by 35.58%, propagation delay by 9.16%, and the number of transistors used compared to the basic logic gate implementation. However, larger buffers were required for output stability in the compound gate schemat

Author

HAROON AHMED

Language

EN