About this document
Fault Tolerant Parallel Filters Design by Thahsin Thahir is a document available to read on EtoBox.
This document describes a fault tolerant parallel filter project based on error correction codes. The project implements a fault tolerant FIR filter on a Xilinx Artix-7 FPGA and utilizes less than 1% of device resources including 514 look-up tables and 111 registers. Simulation results and synthesis reports are provided to analyze the timing constraints, utilization, and performance of the designed filter. Contact information is given to obtain more details on the block diagram, schematic, or simulation res
- Author
- Thahsin Thahir
- Language
- EN