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This document summarizes contributions made to various digital signal processing projects. It describes training sessions conducted on building basic digital logic components like counters and adders in Verilog. It then outlines work done on two projects - Venus (UE) involving RF validation tests at different bandwidths and frequencies, and Jupiter (eNB) involving bringing up an eNB transmitter path and validating different boards. Support was also provided in flashing boards according to requirements.

Author

AkhileshAlexGoyal

Language

EN