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DFT Lab Manual for VLSI Testing by t.r. Santhosh is a document available to read on EtoBox.
What is DFT Lab Manual for VLSI Testing about?
The document provides an overview of a DFT lab manual for a VLSI test seminar. It outlines the objectives and procedures for four labs on scan insertion and DRC analysis, scan compression logic insertion, boundary scan (JTAG 1149.1) implementation, and automatic test pattern generation (ATPG) for stuck-at and transition fault models. Directory structures and commands for invoking various DFT EDA tools are provided for each lab.
- Author
- t.r. Santhosh
- Language
- EN