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Estimating Power in CMOS Circuits by Harsh Gupta is a document available to read on EtoBox.
This paper presents an ILP-based method for estimating the maximum weighted switching activity in combinational CMOS circuits, which is crucial for power dissipation analysis in VLSI designs. The authors utilize advancements in Boolean Satisfiability (SAT) solvers to effectively compute the maximum power dissipation by transforming the problem into an optimization instance. Experimental results demonstrate the effectiveness of the proposed approach in providing accurate power estimates for large circuits.
- Author
- Harsh Gupta
- Language
- EN