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Contents......Page 8 1 Introduction......Page 16 1.1 Research Topics in Reconfigurable Architectures for Embedded Systems......Page 17 1.2 Contributions......Page 20 1.3 Application Specification and Execution on the Zippy Architecture......Page 22 1.4 Preliminary Work at ETH......Page 25 1.5 Thesis outline......Page 26 2 Dynamically Reconfigurable Processor Architecture......Page 28 2.1 Design Objectives......Page 29 2.2.1 Structure......Page 30 2.2.2 Embedded CPU core......Page 31 2.2.3 Reconfigurable Processing Unit......Page 32 2.3 Reconfigurable Processing Unit Architecture......Page 33 2.3.1 Reconfigurable Array......Page 34 2.3.2 FIFOs......Page 39 2.3.4 Context Sequencer and Synchronization......Page 41 2.3.5 Multi-Context Architecture......Page 45 2.3.7 Parameters of the Reconfigurable Processing Unit......Page 46 2.4 Summary......Page 47 3 Tool-Flow......Page 50 3.1 Tool-Flows for Coarse-Grained Reconfigurable Processors......Page 51 3.2 The Zippy Tool-Flow......Page 54 3.3.1 Hardware specification......Page 56 3.3.2 Architecture modeling......Page 58 3.3.3 Placement......Page 61 3.3.4 Routing......Page 64 3.3.5 Configuration Generation......Page 68 3.4.1 Hardware- Softwa

Who reads Hardware Virtualization On A Coarse-grained Reconfigurable Processor (technische Informatik)?

Author

Christian Plessl

Publisher

Shaker Verlag Gmbh, Germany

Published

2006

Language

EN

ISBN

9783832255619

Category

nonfiction

Subjects

Computer Science, Applications & Software, Stem