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What is Power Optimization of LFSR with Clock Gating about?

This document discusses power optimization of linear feedback shift registers (LFSRs) through clock gating. It proposes a modified LFSR design that reduces power consumption by deactivating the clock signal to flip flops when the output signal is the same as the input signal. The power consumption of the new LFSR is reduced due to fewer transitions of the flip flops. It compares the maximum, minimum, and average power of the original and modified LFSR designs to verify the power optimization.

Author

Er Piyush Vyas

Language

EN