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This document describes a dissertation submitted by Jikku Jeemon for the degree of Master of Technology in Embedded System Design. The dissertation details the design of an 8-bit RISC processor using Verilog HDL on an FPGA. It presents the architecture of the proposed processor, which includes features like pipelining, separate instruction and data memory, an 8-bit ALU, registers, interrupts, and I/O ports. The processor is physically verified on a Xilinx Spartan 3E FPGA board running at 25MHz with a supply

Author

Udit Shiradkar

Language

EN