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The document describes a conference paper that proposes an optimized gate diffusion input (OGDI) technique for implementing sequential logic blocks like a sequence detector. OGDI aims to reduce power consumption compared to conventional CMOS logic. It works by adding a regenerator transistor only at the output signal of complex logic circuits. A sequence detector was designed using OGDI and showed over 28% power savings compared to CMOS. Simulation and analysis was done using Cadence Virtuoso at 45nm techno

Author

Shreyas Mahesh

Language

EN