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What is Low-Power 13.7bit NS-SAR ADC Design about?

This paper presents a low-power noise-shaping successive approximation register (SAR) ADC utilizing a split-capacitor DAC, achieving 13.7-bit effective number of bits (ENOB) with an 8KHz bandwidth at a sampling rate of 400KS/s. The design significantly reduces power consumption to only 7.65uW while maintaining high accuracy, making it suitable for biomedical applications. Key components include a passive noise shaping circuit and a two-input dynamic comparator, which contribute to the ADC

Author

ellie2001102

Language

EN